Low-Density Parity-Check (LDPC) codes are one of the most powerful classes of error-control codes known to date. These codes have been 
considered for many recent digital communication applications. In this presentation, we propose stochastic decoding of state-of-the-art 
LDPC codes and demonstrate it as a competitive approach to practical LDPC decoding algorithms. 

In stochastic decoding, probabilities are represented as streams of random bits using Bernoulli sequences in which the information is 
contained in the statistics of the bit stream. This representation results in low hardware-complexity processing nodes that perform 
computationally-intensive operations. However, stochastic decoding is prone to the acute problem of latching. This problem is caused 
by correlated bit streams within cycles in the code's factor graph, and significantly deteriorates the performance of stochastic LDPC decoders. 

We propose edge memories, tracking forecast memories, and majority-based tracking forecast memories to address the latching problem. 
These units efficiently extract the evolving statistics of stochastic bit streams and rerandomize them to disrupt latching. To the best 
of our knowledge, these methods are the first successful methods for stochastic decoding of state-of-the-art LDPC codes. 

We present the ASIC implementation of a stochastic LDPC decoder that decodes the (2048,1723) LDPC code from the IEEE 802.3an standard. 
To the best of our knowledge, this decoder is the most silicon area-efficient and, with a maximum core throughput of 61.3 Gb/s, is one
of the fastest fully parallel soft-decision LDPC decoders reported in the literature. We demonstrate the performance of this decoder in 
low bit-error-rate regimes.