In modern CMOS technology hardware failures occur increasingly more frequently
due to the shortcomings in the hardware design  and adverse physical
conditions.
In order to design reliable communication systems out of unreliable hardware
components, it is imperative to understand the probabilistic performance of
the
known communication algorithms on erroneous hardware. In this paper we offer
an
analysis of the performance of  the nonbinary LDPC decoder that runs Gallager
B
algorithm on an erroneous hardware. We let the check nodes and variable nodes
have different probabilities of error and reveal the dependency of the final
bit
error rate and the error in the computation nodes. Finally we find the
relationship between the size of the underlying field and final bit error
rate.