Conventional coding/communications theory assumes that errors occur during
transmission but that the processing done at the receiver is entirely
noise-free. In the upcoming silicon technologies, however, hardware failures
have emerged as a dominant source of errors. In this work, we analyze a class
of
iterative, graph-based decoding algorithms where we assume that the underlying
processing units experience a certain rate of hardware failures. In
particular,
we study a noisy Gallager B algorithm for decoding regular, irregular and
non-binary LDPC codes. Results of the type presented here could serve as a
starting point in the emerging study of robust inference algorithms
implemented
on practical but imperfect computational units.