The gap between what processors demand and what memory can provide is rapidly widening. Racetrack memory is one of several emerging technologies that aim to close this gap and to replace conventional memories such as DRAM and Flash. It is a non-volatile memory that is engineered to provide both high density and fast read/write speed. However, the potential of racetrack memory technology is compromised by susceptibility to new types of error, namely deletion and repetition. We devise a fast coding solution, in which "delimiter bits" assist in identifying the type of error, and easily implementable graph-based codes are used to correct the error, once identified.